In general, cache is used to duplicate a certain part of main memory, so that the duplicated part in the cache can be accessed by a processor core or a central processing unit (CPU) core in a short amount of time and thus to ensure continued pipeline operation of the processor core.
Currently, cache addressing is based on the following ways. First, an index part of an address is used to read out a tag from a tag memory. At the same time, the index and an offset part of the address are used to read out contents from the cache. Further, the tag from the tag memory is compared with a tag part of the address. If the tag from the tag memory is the same as the tag part of the address, called a cache hit, the contents read out from the cache are valid. Otherwise, if the tag from the tag memory is not the same as the tag part of the address, called a cache miss, the contents read out from the cache are invalid. For a multi-way set associative cache, the above operations are performed in parallel on each set to detect which way has a cache hit. Contents read out from the set with the cache hit are valid. If all sets experience cache misses, contents read out from any set are invalid. After a cache miss, cache control logic fills the cache with contents from lower level storage medium.
Under existing cache structures, various cache prefetching technologies are used to reduce cache miss rate. The cache prefetching technologies can increase certain performance of an instruction cache. However, due to the uncertainty of data addresses in a data cache, it is difficult to effectively predict data addresses in the data cache. Therefore, with the widening gap between the speed of the processor and the speed of the memory, the data cache miss is still a serious bottleneck in increasing the performance of modern processors or computing systems.
The disclosed system and method are directed to solve one or more problems set forth above and other problems.